1. Field of the Invention
This invention relates to cascode cells, and more particularly to cascode cells using heterojunction bipolar transistors.
2. Description of the Related Art
High frequency cascode cells need to have low-inductance interconnects between the two cell transistors while maintaining low capacitive coupling between device terminals. A conventional cascode cell layout may use transistors with terminals ordered in-line as Base-Emitter-Collector (Q1) and Base-Emitter-Collector (Q2). Unfortunately, this configuration leads to a convoluted physical layout that introduces unwanted capacitive coupling and inductance between transistors in the cascode cell. A need continues to exist to reduce capacitive coupling between device terminals and to reduce inductance in transistor interconnects.